1. Field of the Invention
This invention relates to a semiconductor device of one chip containing insulated gate bipolar transistors (IGBTs) and a current limiting circuit for limiting an overcurrent at the load short-circuiting time, etc.
2. Description of the Related Art
For example, as shown in FIG. 6, a semiconductor device comprising a main IGBT 1 and a current limiting circuit 10 on one chip is known as a switching device of a large current and a low saturation voltage (low on voltage). It has an n-channel main IGBT 1, an n-channel sensor IGBT 2 connected in parallel with the main IGBT 1, an emitter resistor RE of the sensor IGBT 2, and an n-channel MOSFET 3 for performing feedback control of a value of gate voltage VG of IGBT when voltage of the emitter resistor RE drops. A gate input signal IN is input to gates G of the main IGBT 1 and the sensor IGBT 2 via an external gate resistor RG connected to a gate terminal A, and VCC power supply is connected to a collector terminal C via a load 6.
By the way, as shown in FIG. 7, the semiconductor structure of the IGBT 1, IGBT 2 has a p.sup.+ -type collector layer (minority carrier injection layer) 12 covered with a collector electrode 11 on the rear face, an n.sup.+ -type buffer layer 13 laminated on the collector layer 12, an n.sup.- -type conductivity modulation layer (n base layer) 14 formed on the buffer layer 13 by epitaxial growth, a polysilicon gate electrode 16 formed on the surface of the conductivity modulation layer 14 via a gate insulating film 15, p-type base layers 17 formed like wells on the surface of the conductivity modulation layer 14 by a self-alignment technique with the gate electrode 16 as a mask, and n.sup.30 -type source layers 19 introduced and formed using aluminum emitter electrodes 18 formed on the base layers 17. In such an IGBT of the semiconductor structure, when a positive potential for the emitter electrode 18 is applied to the gate electrode 16, a channel is formed as an inversion layer on the surface of the p-type base layer 17 as a channel diffusion layer just below the gate electrode 16 and electrons are injected into the conductivity modulation layer 14 via the channel from the emitter electrode 18. In response to this phenomenon, holes are injected into the conductivity modulation layer 14 from the collector layer 12. Thus, the electric conductivity of the conductivity modulation layer 14 abruptly rises, turning on, resulting in a low on voltage.
When the main IGBT 1 is on in the semiconductor device in FIG. 6, if the load 6 is short-circuited, collector current abruptly increases not only in the main IGBT 1, but also in the sensor IGBT 2 parallel with the main IGBT 1. Thus, voltage drop of the emitter resistor RE abruptly rises and the saturation drain current of the MOSFET 3 for gate voltage control increases, discharging gate capacities C1 and C2 of the IGBT 2, thus the gate voltages of the main IGBT 1 and the sensor IGBT 2 abruptly drop. Resultantly, the collector current of the main IGBT 1 and the sensor IGBT 2 abruptly decreases. The reason why the collector current value is limited and a proper amount of current is continued without cutting off the main IGBT 1 when the load is short-circuited is that it is necessary to continue the limit current value without immediately cutting off the main current of the main IGBT 1 in the semiconductor device (chip) until an external protection circuit (not shown) starts operation in response to the short-circuiting of the load.
However, when the load of the IGBT comprising the current limiting circuit 10 is short-circuited, the discharge action of the MOSFET 3 is made dominant and the gate voltage VG is lowered to a predetermined value under the charge action according to the high level voltage of the gate input signal IN of the gate capacity C1, C2 for performing analog current limiting of the IGBT 1, IGBT 2. Thus, the limit current value at the load short-circuiting time varies from one chip to another and the destruction resistance amount to the load short-circuiting largely varies because of resistance value variations of the emitter resistor RE, characteristic variations of the gate voltage control MOSFET 3, temperature characteristic, etc., caused by the current limit action.
To suppress such variations in destruction resistance amounts to the load short-circuiting, a structure for increasing the latch-up resistance amount at the load short-circuiting time, etc., of IGBT rather than building active elements of a feedback loop in one chip is known.
In the IGBT structure shown in FIG. 8A, an emitter electrode 18 is not in direct contact with stripe-like source layers 19 extending in the gate width (channel width) direction of gate electrodes 16 and comes in conductive contact with branch parts 19a extending lice comb teeth from the source layers 19, and diffusion resistance rS is parasitic on each branch part 19a. In such a semiconductor structure in which diffusion resistance rS lies equivalently between the source layers 19 and the emitter electrode 18, if hole current IH flowing into the emitter electrode 18 via just below the source layers 19 in a base layer 17 at the load short-circuiting time abruptly increases and voltage drop of diffusion resistance rB increases, electron current IE flowing through the source layers 19 also abruptly increases at the same time and voltage drop of diffusion resistance rS also increases. Thus, the pn junction of the base layer 17 and the source layer 19 is hard to be forward-biased and parasitic transistor (npn-type transistor consisting of a conductivity modulation layer 14, the base layer 17, and the source layer 19) is hard to latch up. Thus, the destruction resistance amount to load short-circuiting raises.
On the other hand, the IGBT structure shown in FIG. 8B is a structure wherein island-like source layers 19b are formed discretely in the gate width (channel width) direction of gate electrodes 16 and an emitter electrode 18 is formed so as to extend over the source layers 19b; this structure is called a partial channel form structure. In this partial channel form structure, only the hollow portions between the source layers 19b with respect to channels just below the gate electrodes 16 do not conduct with the emitter electrode 18. Resultantly, as in the structure in FIG. 8A, diffusion resistance rS is parasitic between the source layers 19b and the emitter electrode 18, thereby improving the destruction resistance amount to load short-circuiting.
However, even the IGBT structures shown in FIGS. 8A and 8B involve the following problems:
(1) In the overcurrent period such as the load short-circuiting time, the structures are effective for increasing the latch-up resistance amount by an abrupt increase in voltage drop caused by diffusion resistance rS of the source layers 19. However, electron current also flows into diffusion resistance rS in the normal on state and the voltage drop continues. Thus, as a matter of course, on voltage (saturation collector voltage) VCE (sat) raises, increasing an on loss. PA1 (2) Since an abnormal overcurrent of an unknown value may flow at the load short-circuiting time, improvement in the latch-up resistance amount is limited and element destruction may be unable to be prevented.